| Test | Setup | Metric | Result | |------|-------|--------|--------| | | 8 × Megalink 400 GbE modules, 2‑node HPC cluster, iperf3 –t 60 | Sustained TCP | 384 Gbps per link (96 % of line rate) | | Latency | FPGA‑based ping‑pong, 1‑µs timebase | Round‑trip | 84 ns (copper, 5 m) | | BER | 10‑m AOC, PRBS‑31 | Bit Error Rate | ≤ 1 × 10⁻¹⁵ (no errors over 48 h) | | Power | Dynamic load (idle → full) | Power per lane | 0.25 W → 0.78 W | | Thermal | 1U chassis, 25 °C ambient | Junction temperature | ≤ 55 °C (no throttling) | | Hot‑Swap | Live traffic, module removal/re‑insert | Link recovery time | 4.3 ms (auto‑training) |
cp megalink new_megalink
| Component | Description | Key Specs | |-----------|-------------|-----------| | | Dual‑mode (copper/AOC) hot‑swappable module; compliant with SFF‑8615 and SFF‑8644 footprints. | 8 × 50 Gbps or 4 × 100 Gbps per module | | Megalink PCB | Low‑loss FR‑4 with embedded micro‑strip/strip‑line for 28 AWG copper, and fiber‑aligned waveguides for AOC. | Insertion loss < 0.2 dB/10 cm (copper); < 0.1 dB/10 m (AOC) | | Megalink ASIC | 28 nm silicon‑photonic‑compatible die, integrates PAM‑4 modulator, 5‑stage adaptive equalizer, and Reed‑Solomon (RS‑544/514) FEC. | 2.5 ns per lane processing latency | | Connector | MCP‑4 (Megalink Copper/Photonics) – 4‑lane, keyed, self‑aligning. | 0.5 mm pitch, 10 µm insertion tolerance | cp megalink new
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